Western Digital has announced the successful completion of its fifth-generation workflow for 3D NAND memory. Among the features of the new BiCS5 technology is an increased capacity of memory cells, as well as high performance and reliability.
According to Western Digital, the horizontal scaling and application of the 112-layer BiCS5 chip manufacturing technology can not only optimize costs but also create up to 40% more bits for storage per semiconductor wafer compared to 96-layer BiCS4 technology, as well as increase the speed up to 50% work in input/output tasks.
The new technology was developed by the company together with the production partner of Kioxia Corporation. Product manufacturing will be deployed in Japan. Large-scale commercial production starts in the second half of 2020. BiCS5 TLC and BiCS5 QLC memory will be available in various capacities, including 1.33 Tbit.
“In the coming decade, a new approach to scaling 3D NAND memory is urgently needed to further solve problems associated with growing volumes and speed of data processing. The successful development of the BiCS5 process testifies to the leading positions of Western Digital in flash memory technologies and steady progress in the implementation of the technological development plan.
By improving our multi-tier Memory Hole technology, we have increased horizontal density and added additional data storage layers. This allowed us to significantly increase the capacity and performance of 3D NAND memory while maintaining the reliability and cost familiar to our customers, ”said Steve Paak, Senior Vice President, Technology and Production, Western Digital.
BiCS5 expands Western Digital’s portfolio of 3D NAND technologies for information-intensive solutions in consumer electronics, smartphones, IoT devices, and data centres. The technology is based on the use of three-level (TLC) and four-level (QLC) cells, which, according to the vendor, should provide not only a competitive price but also high reliability of products.